module ads8865_driver (
    input   wire            clk,
    input   wire            rst_n,
    input   wire            rd_exec,
    input   wire            din,
    output  reg             convst,
    output  reg             sclk,
    output  reg [ 15:0 ]    rd_data,    
    output  reg             rd_ready,
    output  reg             busy
);

    localparam  st_idle     = 2'b01; 
    localparam  st_read     = 2'b10; 
    reg                     read;
    reg         [ 7:0 ]     clk_cnt;
    wire        [ 2:0 ]     cnt;
    wire                    sclk_gen ;
    reg         [ 3:0 ]     cur_state ;
    reg         [ 3:0 ]     next_state;

    always @(*) begin
    next_state = st_idle;
    case(cur_state)
        st_idle: begin                      
           if(rd_exec) begin
               next_state = st_read;
           end
           else
               next_state = st_idle;
        end
        st_read: begin
            if(rd_ready) 
                next_state = st_idle;
            else
                next_state = st_read ;
        end
    endcase
end

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)
        cur_state <= st_idle;
    else
        cur_state <= next_state;
end


    always@(posedge clk or negedge rst_n)
    begin
        if(!rst_n|!read)
        sclk<=1'b0;
        else
            if(sclk_gen)
                sclk<=~sclk;
    end

    always@(posedge clk or negedge rst_n)
    begin
        if(!rst_n)
            begin
                busy<=1'b0;
                clk_cnt<=8'b0;
                convst<=1'b0;
                read<=1'b0;
                rd_ready<=1'b0;
            end
        else
            begin
                if(sclk_gen)
                    clk_cnt<=clk_cnt+1'b1;
                case(cur_state)
                    st_idle:begin
                        clk_cnt<=8'b0;
                        convst<=1'b0;
                        rd_ready<=1'b0;
                    end
                    st_read:begin
                        read<=1'b1;
                        busy<=1'b1;
                        case(clk_cnt)
                            7'd2:begin
                                convst<=1'b1;
                            end
                            7'd25:begin
                                convst<=1'b0;
                                read<=1'b0;
                            end
                            7'd28:begin
                                read<=1'b1;
                            end
                            7'd60:begin
                                rd_ready<=1'b1;
                                read<=1'b0;
                                busy<=1'b0;
                            end
                            default: ;                   
                        endcase
                    end
                endcase
            end
    end

always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        rd_data      <=16'b0;
    end else begin
    if(rd_exec)
        rd_data      <=16'b0;
        else
        if(cnt==1&&clk_cnt>26&&sclk==1'b1&&read==1'b1)
            rd_data<=(rd_data<<<1)+din;
    end
end


    Counter #(5) sclk_gen_counter (.clk(clk), .rst_n(rst_n), .en( 1'b1), .cnt(cnt),.co(sclk_gen));
endmodule


